Power supply tracking single ended sensing scheme for SONOS memories

ABSTRACT

A SONOS memory sensing scheme includes a reference current circuit that tracks the changes in the power supply (Vcc). An equalizer of the current sense amplifier is coupled between the read out current line and the reference current line. The current sense amplifier includes data and datab (data bar) outputs which have a common mode noise due to variations in the power supply voltage. The data output is a current generated from the memory cell, and the datab output is generated by the current reference circuit.

RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.12/151,282, filed on May 5, 2008, now U.S. Pat. No. 7,995,397, issued onAug. 9, 2011, which claims priority to provisional patent applicationSer. No. 60/927,316, filed on May 3, 2007, both of which are herebyincorporated by reference in their entirety.

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BACKGROUND OF THE INVENTION

SONOS (Silicon Oxide Nitride Oxide Silicon) memories use single endedcurrent sensing to reduce chip area. SONOS bi-gate memory cells includea pass transistor and a SONOS cell. The read current of the memory cellis modulated by VCC significantly (up to, for example, 8 uA/V) due tothe pass transistor's VCC dependence. This causes read failures due tosignificant degradation of sense margin. A conventional solution uses adouble ended sensing scheme to track VCC dependence. Since there is noreference current involved and the current modulation due to passtransistors is a common mode signal for the bitline and the bitline-barside, the VCC modulation effect on the final read speed and sense marginis removed. Unfortunately, these sort of differential read schemesinvolve two cells per bit of storage leading to poor area efficiency.

Another conventional solution uses a single ended sensing scheme with apair of dummy column memory cells (one column for program cells and onecolumn for erase cells) for every block of the array to obtain areference current. The currents from the dummy columns of memory cellswhen added together can be mirrored to supply a reference cell currentthat is the center of program and erase current. Since the VCCmodulation due to the pass transistor is common mode for the dummycolumns of memory cells and the cell being accessed, the final readspeed and sense margin were unaffected by pass transistor VCCmodulation. Unfortunately, single ended sensing schemes that use a pairof dummy column cells to generate a reference current are less efficientin terms of chip area than a single ended sensing scheme that does notuse dummy column of cells

Non-volatile memories that use single ended sensing schemes need acurrent sensing scheme that automatically tracks the VCC modulation ofthe memory cell to achieve better sense margin and high speed sensing.

BRIEF SUMMARY OF INVENTION

A SONOS memory sensing scheme includes a reference current circuit thattracks the changes in the power supply (Vcc). An equalizer of thecurrent sense amplifier is coupled between the read out current line andthe reference current line. The current sense amplifier includes dataand datab (data bar) outputs which have common mode noise due tovariations in the power supply voltage. The data output is a currentgenerated from the memory cell, and the datab output is generated by thecurrent reference circuit.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a circuit diagram of a SONOS memory sensing scheme inaccordance with one embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to a SONOS memory sensing scheme thathas a reference current circuit that tracks the changes in the powersupply (Vcc). An equalizer of the current sense amplifier is coupledbetween the read out current line and the reference current line. Thecurrent sense amplifier includes data and datab (data bar) outputs whichcontain the common mode noise due to variations in the power supplyvoltage. The data output is a current generated from the memory cell,and the datab output is generated by the current reference circuit.

FIG. 1 is a circuit diagram of a SONOS memory sensing scheme 10 inaccordance with one embodiment of the invention. The sensing scheme 10has three main elements: a non-volatile (NV) memory array 12; a currentsense amplifier 14; and a current reference circuit 16. The NV memoryarray 12 includes any suitable number of columns of memory cells, ofwhich only a portion of one column is shown for purposes of illustrationand not limitation. The NV memory array 12 shows a column of passtransistors 18, 20, 22, which are labeled, MPASS0, MPASS1, MPASSn (wheren can be any suitable number). The gates 24, 26, 28 of the passtransistors 18, 20, 22 are coupled to the word lines WL0, WL1, WLn,respectively. The drains 30, 32, 34 of the pass transistors 18, 20, 22are coupled to the sense line (SL) 36. The sources of the passtransistors 18, 20, 22 are coupled to the drains of the SONOStransistors 38, 40, 42. The SONOS transistors 38, 40, 42 are labeledMSONOS1, MSONOS2, MSONOSn. The gates 44, 46, 48 of the SONOS transistors38, 40, 42 are coupled to SONOS word lines, WLS0, WLS1, WLSn,respectively. The sources of the SONOS transistors 38, 40, 42 arecoupled to the bit line (BL). A column multiplexer 52 couples the bitline 50 to the current sense amplifier 14, although the columnmultiplexer 52 is capable of coupling one of a plurality of bit lines inthe NV memory array 12 to the current sense amplifier 14.

The current sense amplifier 14 includes PMOS transistor (MP1) 54 with asource 56 coupled to the power supply voltage (Vcc) 58. The gate 60 oftransistor 54 is coupled to an enable signal (saenb). The drain 62 oftransistor 54 is coupled to the first nodes of a pair of loads 64, 66.An equalization circuit 68 is coupled between the second nodes of theloads 64, 66. The equalization circuit 68 is controlled by an enablesignal (saeq) 70. The load 64 is coupled to the data output line 72 andto the column multiplexer 52, and the current from the memory cell(Icell) is carried by this conductor. The load 66 is coupled to thedatab output line 74 and to the drain 76 of NMOS transistor (MN2) 78.The source 80 of transistor 78 forms the signal Iref2 and is coupled tothe drain 82 of NMOS transistor (MPASSR) 84. The source 86 of transistor84 is coupled to the low voltage of the power supply (VSS) 88. The gate90 of transistor 84 is coupled to the high voltage of the power supply(VCC) 58. The gate 92, labeled nbias, of transistor 78 is coupled to thecurrent reference circuit 16.

The current reference circuit 16 includes a current source (Iref) 94coupled to the power supply voltage 58. The output of the current source94 is coupled to the drain 96 and gate 98 of NMOS transistor (MN1) 100.The source 102 of transistor 100 is coupled to the low voltage of thepower supply (VSS) 88. Thus, the current reference circuit 16 isconfigured to create a suitable bias at the gate 98 of transistor MN1100 for a given reference current (Iref1).

The current sense amplifier 14 shown in FIG. 1 takes in the current(Icell) from the NV memory array 12 and compares it to the referencecurrent (Iref2) and outputs a differential voltage output voltage(data-datab) which can be further amplified by downstream voltageamplifiers. When the input saenb 60 is low, it turns on the currentsense amplifier 14 by turning ON transistor MP1 54. Input saeq 70comprises an enable to the equalization circuit 68 to help precharge andequilibrate the differential nodes prior to turn ON of the current senseamplifier 14. The loads 64, 66 serve as the loading devices for thecurrent sense amplifier 14. The loads 64, 66 can be designed using, forexample, diode connected devices, resistors, current mirror loads,biased transistors, or the like. Transistor MN2 78 comprises a mirror oftransistor MN1 100, but with its source degenerated by the Vds drop oftransistor MPASSR 84. Transistor MPASSR 84 comprises a replica of thePASS transistors 18, 20, 22 in the NV memory array 12 which sees a powersupply bias on its gate during a read operation.

For purposes of illustration and not limitation, during a read operationrow0 is selected by taking WL0=VCC, SL=0 and WLS0=0. The columnmultiplexer 52 is turned ON by a column address. This causes the currentIcell to flow through the bitlines, colmux and the sense amplifier loadsto VCC. Since WL=VCC, the current Icell is modulated by a change in thepower supply voltage VCC. In the reference side, the Iref1 current isset by the current source 94 to give a bias that will create a currentthat is, for example, approximately 0.5*(Iers+Iprg), where Iers is theworst case erase current and Iprg is the worst case program current.Gate 92 of transistor MN2 78 gets this bias voltage set at the gate 98of transistor MN1 100, but also has its source degenerated by a replicaPASS transistor MPASSR 84. The Vds drop across MPASSR 84 degenerates thesource 80 of transistor MN2 78 such that Iref2 is also modulated due topower supply variation, and, thus, tracks the cell current modulation.Since the current is affected on both sides of the amplifier, thisbecomes common mode and results in very good sense margin and readspeeds across power supply variations.

The new amplifier according to exemplary embodiments of the presentinvention achieves robust and accurate power supply tracking through theuse of a replica PASS transistor 84 in the current sense amplifier 14.The present new sense read scheme is area efficient, because it does notuse an entire column of dummy cells. In addition, the new schemeachieves good sense margin and read speeds even for wide variation ofpower supply voltage.

Exemplary embodiments of the present invention can be used inconjunction with any suitable type of memory, such as, for example,non-volatile SONOS memory technologies or products, or other likememories. Each of elements of the circuit 10 can be comprised of anysuitable type of electrical or electronic circuit, component or devicethat is capable of performing the functions associated with therespective element. For example, each of the transistors illustrated inFIG. 1 can be comprised of any suitable type of transistor or other likedevice.

While the invention has been described in conjunction with specificembodiments thereof, it is evident that many alterations, modifications,and variations will be apparent to those skilled in the art in light ofthe foregoing description. Accordingly, it is intended to embrace allsuch alterations, modifications, and variations in the appended claims.

1. A method comprising: coupling a cell current (Icell) from a memorycell in a memory array to a first input of a single-ended current senseamplifier, wherein Icell is modulated by a change in a high voltagesupply (VCC) to the memory array; coupling a bias voltage from a currentreference circuit to a gate of a transistor in a second input of thecurrent sense amplifier to couple a reference current (Iref) to thesecond input, the transistor comprising a source coupled to a lowvoltage supply (VSS) through a replica pass transistor; and degeneratingthe source of the transistor with the replica pass transistor tomodulate Iref to track changes in VCC.
 2. The method of claim 1, whereindegenerating the source of the transistor comprises degenerating thesource of the transistor with the replica pass transistor.
 3. The methodof claim 2, wherein the replica pass transistor comprises a gate coupledto VCC, and wherein degenerating the source of the transistor with thereplica pass transistor comprises changing a drain to source voltageacross the replica pass transistor.
 4. The method of claim 1, whereinthe transistor in the second input is a mirror transistor mirroring acurrent through a bias transistor in the current reference circuit. 5.The method of claim 4, wherein the bias voltage from the currentreference circuit is selected to provide an unmodulated Iref through themirror transistor is substantially centered between a program currentand an erase current.
 6. The method of claim 5, wherein the bias voltagefrom the current reference circuit is selected to provide an unmodulatedIref through the mirror transistor of one half a sum of a worst caseerase current and worst case program current.
 7. The method of claim 5,wherein coupling Icell to the first input comprises coupling Icell to afirst load in the first input, and coupling Iref to the second inputcomprises coupling Iref to the second input through a second load. 8.The method of claim 7, wherein the current sense amplifier furthercomprises an equalizer circuit coupled between the first load and thesecond load, and wherein the method further comprises reducing with theequalizer circuit a differential between the first load and the secondload prior to coupling Icell to the first input or coupling the biasvoltage to the gate of the mirror transistor in the second input.
 9. Amethod comprising: precharging a first load in a first input and asecond load in a second input of a current sense amplifier for anon-volatile memory; biasing a transistor in the second input to inducea reference current (Iref) to the second input; coupling a cell current(Icell) from a memory cell in a memory array to the first input, whereinIcell is modulated by a change in a high voltage supply (VCC) to thememory array; and degenerating the source of the transistor to modulateIref to track changes in VCC, wherein the transistor in the second inputcomprises a source coupled to a low voltage supply (VSS) through areplica pass transistor, and wherein degenerating the source of thetransistor comprises degenerating the source of the transistor with thereplica pass transistor.
 10. The method of claim 9, wherein the replicapass transistor comprises a gate coupled to VCC, and whereindegenerating the source of the transistor with the replica passtransistor comprises changing a drain to source voltage across thereplica pass transistor in response to changes in VCC.
 11. The method ofclaim 9, wherein the transistor in the second input is a mirrortransistor mirroring a current through a bias transistor in a currentreference circuit supplying the bias voltage to the mirror transistor.12. The method of claim 11, wherein the bias voltage from the currentreference circuit is selected to provide an unmodulated Iref through themirror transistor substantially centered between a program current andan erase current.
 13. The method of claim 11, wherein the bias voltagefrom the current reference circuit is selected to provide an unmodulatedIref through the mirror transistor of one half a sum of a worst caseerase current and worst case program current.
 14. A sensing apparatusfor non-volatile memories, comprising: a single-ended current senseamplifier; a column multiplexer coupled to a first input of the currentsense amplifier and to a memory array; and a current reference circuitand a replica pass transistor coupled to a second input of thesingle-ended current sense amplifier.
 15. The apparatus of claim 14,wherein the single-ended current sense amplifier comprises a first loadcoupled to the column multiplexer and a second load in parallel with thefirst load coupled to the current reference circuit.
 16. The apparatusof claim 15, wherein the second load is coupled through a mirrortransistor to the replica pass transistor.
 17. The apparatus of claim16, wherein the memory array includes a bitline output coupled to thecolumn multiplexer.
 18. The apparatus of claim 17, wherein the memoryarray comprises a pass transistor in series with a memory transistor.19. The apparatus of claim 15, further including an equalizer circuitcoupled between the first load and the second load.